6 points, SCA Band 2, 0.125 EFTSL
Undergraduate - Unit
Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.
Faculty
Organisational Unit
Department of Electrical and Computer Systems Engineering
Chief examiner(s)
Coordinator(s)
Assoc Professor Lindsay Kleeman
(Clayton)
Dr Patrick Ho
(Malaysia)
Unit guides
Prerequisites
24 credit points from the Faculty of Engineering or the Faculty of Information Technology
Prohibitions
ECE2701, TEC2172, TRC2300
Synopsis
This unit introduces the student to modern logic design techniques, hardware used and common representations. Topics include two and multi-level combinational logic, decoders, multiplexers, arithmetic circuits, programmable and steering logic, flip-flops, registers, counters, RAM and ROM. Using this hardware the design component will include finite state machine design and applications to computer data path control. This will incorporate simple analogue and digital I/O interfacing. Programmable logic devices will be covered, and the use of a hardware description language for describing, synthesising and testing digital logic. Laboratories cover logic design, implementation, and testing.
Outcomes
On successful completion of this unit, students will be able to:
- Apply different techniques such as K-map and Quine McCluskey, to minimise logic expressions and implement them using primitive logical gates.
- Analyse the operation of latches, flip-flops, multiplexors, decoders, counters, registers and use them in implementing complex digital systems.
- Design and build complex digital systems using programmable logic devices such as PLAs, PALs and FPGAs.
- Use a Hardware Description Language and Computer Aided Design Tools to synthesise and simulate logic circuits in a clear, consistent and efficient manner.
- Analyse and design finite state sequential Mealy and Moore machines and implement them using different technologies.
- Define time delays of digital logic elements and explain timing constraints necessary for correct operation of synchronous logic.
Assessment
NOTE: From 1 July 2019, the duration of all exams is changing to combine reading and writing time. The new exam duration for this unit is 2 hours and 10 minutes.
Continuous assessment: 40%
Examination (2 hours): 60%
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.
Workload requirements
3 hours lectures, 3 hours laboratory and practice classes and 6 hours of private study per week
See also Unit timetable information