Faculty of Engineering

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This unit entry is for students who completed this unit in 2016 only. For students planning to study the unit, please refer to the unit indexes in the the current edition of the Handbook. If you have any queries contact the managing faculty for your course or area of study.

Monash University

6 points, SCA Band 2, 0.125 EFTSL

Undergraduate - Unit

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.



Organisational Unit

Department of Electrical and Computer Systems Engineering


Dr David Boland (Clayton); Nader Kamrani (Malaysia)



  • First semester 2016 (Day)


  • First semester 2016 (Day)


This unit provides an introduction to computer architecture using a modern microprocessor as an example. Practical considerations involved in interconnecting logic element are explored, along with software and hardware techniques for interfacing computers to peripheral devices. An introduction to communication protocols used to connect local peripheral devices to a microprocessor, including RS232/RS422/RS485, CAN bus and i2C is provided. Real time systems including concurrency, inter-process communications and scheduling are introduced.


At the end of this unit, students should be able to:

  • describe the organisation and operation of an embedded (computer) system, microprocessor, the system bus, memory hierarchy, and peripherals
  • design and evaluate performance of programs in C and/or assembly to process data from peripheral devices
  • explain different conversion techniques between analogue and digital signals and different serial communication protocols
  • analyse and compare behaviour of different real time schedulers
  • analyse, design and test real time software employing concurrency and inter-process communication
  • explain the process of compiling a high level language program


Laboratory and assignment work: 30%
Examinations (3 hours): 70%.
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.

Workload requirements

Two 1 hour lectures, one 3 hour laboratory/practice class and 7 hours of private study per week

See also Unit timetable information

Chief examiner(s)


ECE2072 and one of:
+ ECE2071
+ FIT1008
+ FIT1029 and FIT1040


ECE3703, GSE2303, GSE3802, TEC3174, TRC3300