Faculty of Engineering

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This unit entry is for students who completed this unit in 2016 only. For students planning to study the unit, please refer to the unit indexes in the the current edition of the Handbook. If you have any queries contact the managing faculty for your course or area of study.

Monash University

6 points, SCA Band 2, 0.125 EFTSL

Undergraduate - Unit

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.



Organisational Unit

Department of Electrical and Computer Systems Engineering


Dr David Boland Clayton); Mr Nader Kamrani (Malaysia)



  • Second semester 2016 (Day)


  • Second semester 2016 (Day)


This unit introduces the student to modern logic design techniques, hardware used and common representations. Topics include two and multi-level combinational logic, decoders, multiplexers, arithmetic circuits, programmable and steering logic, flip-flops, registers, counters, RAM and ROM. Using this hardware the design component will include finite state machine design and applications to computer data path control. This will incorporate simple analogue and digital I/O interfacing. Programmable logic devices will be covered, and the use of a hardware description language for describing, synthesizing and testing digital logic. Laboratories cover logic design, implementation, and testing.


On successful completion of this unit, students will be able to:

  1. Apply different techniques such as K-map and Quine McCluskey, to minimize logic expressions and implement them using primitive logical gates.
  2. Analyse the operation of latches, flip-flops, multiplexors, decoders, counters, registers and use them in implementing complex digital systems.
  3. Design and build complex digital systems using programmable logic devices such as PLAs, PALs and FPGAs.
  4. Use a Hardware Description Language and Computer Aided Design Tools to synthesise and simulate logic circuits in a clear, consistent and efficient manner.
  5. Analyse and design finite state sequential Mealy and Moore machines and implement them using different technologies.
  6. Define time delays of digital logic elements and explain timing constraints necessary for correct operation of synchronous logic.


Laboratory and assignment work: 30%
Examination (3 hours): 70%
Students are required to achieve at least 45% in the total continuous assessment component (assignments, tests, mid-semester exams, laboratory reports) and at least 45% in the final examination component and an overall mark of 50% to achieve a pass grade in the unit. Students failing to achieve this requirement will be given a maximum of 45% in the unit.

Workload requirements

3 hours lectures, 3 hours laboratory and practice classes and 6 hours of private study per week

See also Unit timetable information

Chief examiner(s)


ECE2701, TEC2172, TRC2300