Monash University Handbook 2011 Undergraduate - Unit

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.

Synopsis

This unit covers the internal mechanism of computers and how they are organised and programmed. Topics include combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, counters, ripple adders, tree adders, memory/addressing, busses, speed, DMA, data representation, machine arithmetic, microprogramming, caches and cache architectures, virtual memory and translation look-aside buffers, vectored interrupts, polled interrupts, pipelined architecture, superscalar architecture, data dependency, hazards, CISC, RISC, VLIW machine architectures.

Objectives

At the completion of this unit students will have -
A knowledge and understanding of:

• combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, and hazards;
• counters, ripple adders, tree adders, memory/addressing, computer busses, logic and bus speed, and Direct Memory Access;
• data representation for integers and floating point operands;
• machine arithmetic, microprogramming;
• storage herarchies, caches and cache architectures, performance impact of caching;
• virtual memory and translation look-aside buffers, performance impact of TLB caching;
• vectored and polled interrupt handling;
• pipelined architecture, superscalar architecture, data dependency, and hazards;
• CISC, RISC, VLIW machine architectures.

• model combinatorial and sequential logic circuits using a simulator tool;
• perform programming tasks in assembly code.

Assessment

Examination (3 hours): 60%; In-semester assessment: 40%

Chief examiner(s)

Dr Carlo Kopp

Contact hours

2 hrs lectures/wk, 3 hr laboratory/fortnight, 1 hr tutorial/fortnight

Prerequisites

FIT1031 or FIT1001 and FIT1008 or FIT1015

Additional information on this unit is available from the faculty at:

http://www.infotech.monash.edu.au/units/fit2069.html