units

ECE2072

Faculty of Engineering

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Monash University

Monash University Handbook 2011 Undergraduate - Unit

6 points, SCA Band 2, 0.125 EFTSL

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered.

LevelUndergraduate
FacultyFaculty of Engineering
OfferedClayton Second semester 2011 (Day)
Sunway Second semester 2011 (Day)
Coordinator(s)L Kleeman (Clayton); M Ooi (Sunway)

Synopsis

This unit introduces the student to modern logic design techniques, hardware used and common representations. Topics include two and multi-level combinational logic, decoders, multiplexers, arithmetic circuits, programmable and steering logic, flip-flops, registers, counters, RAM and ROM. Using this hardware the design component will include finite state machine design and applications to computer data path control. This will incorporate simple analogue and digital I/O interfacing. Programmable logic devices will be covered, and the use of a hardware description language for describing, synthesizing and testing digital logic. Laboratories cover logic design, implementation, and testing.

Objectives

To understand the analysis and design of complex digital systems from building blocks, using modern digital design software.

Assessment

Laboratory and assignment work: 30%
Examination (3 hours): 70%. Student must achieve a mark of 45% in each component to achieve an overall pass grade.

Chief examiner(s)

Professor Arthur Lowery

Contact hours

3 hours lectures, 3 hours laboratory and practice classes and 6 hours of private study per week

Prohibitions

ECE2701, TEC2172, TRC2300