units

FIT2069

Faculty of Information Technology

18 September 2017 22 November 2024
Monash University

Undergraduate - Unit

This unit entry is for students who completed this unit in 2014 only. For students planning to study the unit, please refer to the unit indexes in the the current edition of the Handbook. If you have any queries contact the managing faculty for your course or area of study.

print version

6 points, SCA Band 2, 0.125 EFTSL

Refer to the specific census and withdrawal dates for the semester(s) in which this unit is offered, or view unit timetables.

LevelUndergraduate
FacultyFaculty of Information Technology
OfferedClayton First semester 2014 (Day)

Synopsis

This unit covers the internal mechanism of computers and how they are organised and programmed. Topics include combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, counters, ripple adders, tree adders, memory/addressing, busses, speed, DMA, data representation, machine arithmetic, microprogramming, caches and cache architectures, virtual memory and translation look-aside buffers, vectored interrupts, polled interrupts, pipelined architecture, superscalar architecture, data dependency, hazards, CISC, RISC, VLIW machine architectures.

Outcomes

At the completion of this unit students will have -

A knowledge and understanding of:

  • combinatorial and sequential logic, Boolean Algebra, Karnaugh maps, and hazards;
  • counters, ripple adders, tree adders, memory/addressing, computer busses, logic and bus speed, and Direct Memory Access;
  • data representation for integers and floating point operands;
  • machine arithmetic, microprogramming;
  • storage hierarchies, caches and cache architectures, performance impact of caching;
  • virtual memory and translation look-aside buffers, performance impact of TLB caching;
  • vectored and polled interrupt handling;
  • pipelined architecture, superscalar architecture, data dependency, and hazards;
  • CISC, RISC, VLIW machine architectures.

Developed the skills to:

  • model combinatorial and sequential logic circuits using a simulator tool;
  • perform programming tasks in assembly code.

Assessment

Examination (3 hours): 60%; In-semester assessment: 40%

Chief examiner(s)

Dr Carlo Kopp

Workload requirements

Minimum total expected workload equals 12 hours per week comprising:

(a.) Contact hours for on-campus students:

  • Two hours of lectures
  • One 3-hour laboratory or one 2-hour tutorial (alternating weeks)

(b.) Additional requirements (all students):

  • A minimum of 7-8 hours independent study per week for preparing for and completing lab and project work, private study and revision.

This unit applies to the following area(s) of study

Software engineering
Systems development

Prerequisites

FIT1031 or FIT1001 and FIT1008 or FIT1015

Additional information on this unit is available from the faculty at:

http://www.infotech.monash.edu.au/units/fit2069.html