ECE4063 - Large scale digital design

Offered

Clayton First semester 2008 (Day)
Sunway First semester 2008 (Day)

Synopsis

The unit aims to develop a fundamental understanding of the performance, specification and fabrication of large scale digital circuits. Students will become experienced at the design, simulation, verification and debugging of complex large scale digital circuits using a Hardware Description Language (HDL) and current CAD tools with FPGA development boards. Two group design projects will be undertaken: one involving an HDL using FPGA devices and another involving custom VLSI CMOS design and simulation

Objectives

• understand the evolution of complex digital integrated circuits and scaling issues
• appreciate the fabrication processes used for producing CMOS VLSI circuits
• understand of the uses and limitations of VLSI and HDL in the synthesis and simulation
• develop an appreciation of different VLSI design styles and hierarchical design
• gain a physical insight into digital circuit behaviour and performance
• appreciate the characteristics of synchronous and self-timed design methodologies
• understand the fundamental synchronization issues of independent digital systems
• develop skills in VLSI and HDL large scale digital design and simulation with CAD tools
• acquire the skill of debugging and fault finding large scale digital designs
• appreciate how fundamentals of digital design can be applied to this rapidly changing field

Assessment

Laboratory and assignment work: 40%
Examination (3 hours): 60%. Students must achieve a mark of 45% in each component and an overall mark of 50% to achieve an overall pass grade.

Contact hours

2 hours lectures, 3 hours laboratory/practice classes and 7 hours private study per week

Prerequisites

ECE2062

Co-requisites

ECE3073

Prohibitions

ECE4604, ECE5063, ECE5604