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ECE3703 - Computer engineering

4 points, SCA Band 2, 0.083 EFTSL

Undergraduate Faculty of Engineering

Leader: G Egan


Malaysia First semester 2007 (Day)


The design and implementation of common digital logic families and practical considerations in logic design including design for testability asynchronous logic design, noise margin and timing constraints. A simple microprocessor architecture is introduced and this material is extended to consider how a microprocessor, memory and other peripheral circuits are connected to form a working system. The software and hardware required to interface a computer to the outside world are examined.


Examination (3 hours): 70%
Laboratory and assignment work: 30%

Contact hours

26 hours of lectures and 24 hours of practice classes and laboratory classes


ECE2701 and ECE2702 (or CSE1303)